Turning a natural-language hardware request into verified RTL — and keeping what's measured separate from what's guessed

At the Inference-Time Compute Hackathon, my teammates and I built Fairchild, a tuned chip-design model paired with an evaluation-native IDE. You type a natural-language hardware request, and the system turns it into a structured spec, extracts the compute kernels, proposes hardware candidates, estimates how the workload runs on each, generates real RTL for the winner, verifies that RTL with Verilator, and writes an evidence-backed report. You can read more on the Devpost.

The Problem

Generic LLMs are bad at hardware design. They produce confidently incorrect RTL that is hard to validate, blurring the line between numbers the model guessed and numbers a tool actually measured. Fairchild's core idea is to keep those two things visually and verbally separate everywhere: every estimated performance number is tagged [ESTIMATE], and every tool-verified result is tagged [MEASURED].

How It Works

The system is two layers:

• The model: Qwen2.5-Coder-7B-Instruct, fine-tuned with QLoRA for Verilog generation and tool-error repair, measured on a held-out benchmark as base vs. tuned vs. tuned+repair.
• The IDE: a Streamlit app that drives a staged pipeline and shows the tuned model working inside a verification-driven loop. The model proposes, the tools evaluate, and the IDE explains.

The pipeline runs as a sequence of grounded stages: a natural-language prompt is compiled into a structured spec, the spec's compute kernels are extracted, hardware candidates are generated and ranked under the stated constraints, RTL is generated for the winning candidate, and Verilator lints that RTL to produce a measured result rather than an estimated one.

What I Worked On

My focus was the model training side — the QLoRA fine-tuning of Qwen2.5-Coder for Verilog generation and RTL repair, and the benchmark that proves the tuned model actually beats the base model. This was built together with Eva Zhu, Yeabsira Teshome, and Arpit Khandelwal.

Results

Post-training clearly helped. On the held-out SFT validation split, the tuned LoRA adapter roughly halved the eval loss (0.490 → 0.245), dropped perplexity from 1.63 to 1.28, and improved next-token accuracy by ~4 percentage points (88.6% → 92.7%) — all from a single ~4-hour run on one H100.

What matters more than LM loss, though, is whether the generated RTL actually compiles and passes testbenches. On a held-out set of 155 VerilogEval spec-to-RTL tasks scored with Icarus/Verilator, the tuned model (v5) beat the base model across the board — compile pass rate 0.81 → 0.89, functional test pass 0.35 → 0.38, and pass@3 0.46 → 0.50.

Grounding in the Literature

The design draws on two papers: ChipNeMo shows generic LLMs are weak at chip design and that domain adaptation plus grounded evaluation is what moves the needle, and NL2GDS argues natural-language-to-chip should be a staged flow with tool feedback and iterative repair. Fairchild is our attempt to put both lessons into a single working product.

Check out the project: github.com/rishabhranawat/chips. You can also browse the full hackathon slide deck.